`include "ascon_define.v"

module `ASCON_AEAD_AD
(
     input                                       ascon_aead_clk_i,                      //其中a的含义为ascon_aead，代表该时钟域
     input                                       ascon_aead_rst_n_i,

     input                                       ascon_aead_ad_vld_i,
     input                                       ascon_aead_ad_en_i,
     input                                       ascon_aead_ad_mode_i,
     input                            [`A_W-1:0] ascon_aead_ad_a_i,
     input                            [`S_W-1:0] ascon_aead_ad_s_i,

     output                           [`S_W-1:0] ascon_aead_ad_s_o,
     output                                      ascon_aead_ad_vld_o
);
//外信号

wire                                             vld_i_p;
wire                                             en_p;
wire                                             mode_p;
wire                                  [`A_W-1:0] a_p;
wire                                  [`S_W-1:0] s_i_p;
wire                                  [`S_W-1:0] s_o_p;
wire                                             vld_o_p;
//接口信号
wire                                  [`S_W-1:0] n_s_w;
wire                                  [`S_W-1:0] a_s_w;
wire                                  [`S_W-1:0] s_i0_w;
wire                                  [`S_W-1:0] s_o0_w;
wire                                  [`S_W-1:0] s_i1_w;
wire                                  [`S_W-1:0] s_o1_w;
wire                                             vld_w;
//连接接口信号

assign vld_i_p               = ascon_aead_ad_vld_i;
assign en_p                  = ascon_aead_ad_en_i;
assign mode_p                = ascon_aead_ad_mode_i;
assign a_p                   = ascon_aead_ad_a_i;
assign s_i_p                 = ascon_aead_ad_s_i;

assign ascon_aead_ad_s_o     = s_o_p;
assign ascon_aead_ad_vld_o   = (mode_p == 1'b0) ? vld_w : vld_o_p;

//接口信号 生成

assign n_s_w                 = {a_p,256'b0} ^ s_i_p;
assign a_s_w                 = {a_p,1'b1,255'b0} ^ s_i_p;
assign s_i0_w                = (mode_p == 1'b0) ? a_s_w : n_s_w;

assign s_i1_w                = s_o0_w ^ {1'b1,319'b0};
assign s_o_p                 = (mode_p == 1'b0) ? s_o0_w ^ {319'b0,1'b1} : s_o1_w ^ {319'b0,1'b1};
`P6_8
u0_p6_8
    (
    .clk_i                             (ascon_aead_clk_i                       ),
    .rst_n_i                           (ascon_aead_rst_n_i                     ),
    .p6_8_en_i                         (en_p                                   ),
    .p6_8_mode_i                       (mode_p                                 ),
    .p6_8_vld_i                        (vld_i_p                                ),
    .p6_8_s_i                          (s_i0_w                                 ),
    .p6_8_s_o                          (s_o0_w                                 ),
    .p6_8_vld_o                        (vld_w                                  )
    );

`P6_8
u1_p6_8
    (
    .clk_i                             (ascon_aead_clk_i                       ),
    .rst_n_i                           (ascon_aead_rst_n_i                     ),
    .p6_8_en_i                         (en_p                                   ),
    .p6_8_mode_i                       (mode_p                                 ),
    .p6_8_vld_i                        (vld_w                                  ),
    .p6_8_s_i                          (s_i1_w                                 ),
    .p6_8_s_o                          (s_o1_w                                 ),
    .p6_8_vld_o                        (vld_o_p                                )
    );

endmodule